"System-Level &RTL
Design: More and more projects are starting
with a system-level design (SLD). Reasons
for performing a SLD is to ensure software/hardware
verification or to assess performance of
the
overall architecture or key algorithms. ModelSim's
single-kernel architecture provides a unified
kernel for Verilog, VHDL, and SystemC 2.1,
for a true, mixed-language environment."